The present invention relates to a semiconductor integrated circuit device and a method of designing the same semiconductor integrated circuit device and particularly to a technique which can be effectively applied to the operation test technique of an internal logic circuit.
Supply of clock from an external circuit cannot be controlled for a digital integrated circuit device comprising a built-in pulse generating circuit such as a PLL circuit. Therefore, in the AC (Alternate Current) operation test of an internal logic circuit, it is considered to provide a combination circuit as illustrated in FIG. 17 in order to control the clock pulse to be supplied to the internal logic circuit. Namely, here is introduced the sequence that a test pattern is set to a flip-flop FF of the logic circuit using a scanning circuit, a combination circuit is controlled to output the first clock pulse to transfer an input signal to the logic stage and generate the second clock pulse, and an output signal of the logic stage is fetched by the flip-flop FF and a test result is collected using the scanning circuit. The Japanese Unexamined Patent Application Publication 1999(11)-142478 discloses an example of a semiconductor integrated circuit which comprises a clock multiplying circuit within a chip thereof in order to execute the test during the actual operation.